ICS673-01 Datasheet, PDF (3/9 Pages) Integrated Circuit Systems – PLL Building Block

ICS673-01
PLL Building Block
Electrical Specifications
Parameter
Conditions
ABSOLUTE MAXIMUM RATINGS (note 1)
Minimum Typical Maximum Units
Supply voltage, VDD
Referenced to GND
Inputs and Clock Outputs
Referenced to GND
-0.5
Ambient Operating Temperature
ICS673M-01
0
ICS673M-01I
-40
Soldering Temperature
Max of 10 seconds
Storage temperature
-65
DC CHARACTERISTICS (VDD = 5.0 V unless noted)
7
V
VDD+0.5 V
70
°C
85
°C
260
°C
150
°C
Operating Voltage, VDD
3.13
Input High Voltage
All except VCOIN
2
Input Low Voltage
All except VCOIN
Input High Voltage
VCOIN
Input Low Voltage
VCOIN
0
Output High Voltage, VOH
IOH=-25mA
2.4
Output Low Voltage, VOL
IOL=25mA
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
Operating Supply Current, IDD
No Load,CLK1=40MHz
15
Power Down Supply Current, IDDPD
No Load
6
Short Circuit Current
Each output
±100
Input Capacitance
OE, PD, SEL
5
AC CHARACTERISTICS (VDD = 5.0 V unless noted)
5.50
V
V
0.8
V
VDD
V
V
V
0.4
V
V
mA
µA
mA
pF
Output Clock Frequency (4.5 to 5.5 V)
Output Clock Frequency (3.13 to 3.46 V)
CLK1 and CLK2 skew
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
VCO Gain, Kv
Charge Pump Current, Ic
CLK1 with SEL=1
2
CLK1 with SEL=1
2
Rising edges at VDD/2
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
45
135
MHz
100
MHz
500
ps
1.5
ns
1.5
ns
50
55
%
95
MHz/V
2.4
µA
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
MDS 673-01 D
3
Revision 022500
Printed 11/15/00
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