ICS673-01 Datasheet, PDF (1/9 Pages) Integrated Circuit Systems – PLL Building Block

ICS673-01
PLL Building Block
Description
The ICS673-01 is a low cost, high performance
Phase Locked Loop (PLL) designed for clock
synthesis and synchronization. Included on the
chip are the phase detector, charge pump, Voltage
Controlled Oscillator (VCO), and two output
buffers. One output buffer is a divide by two of
the other. Through the use of external reference
and VCO dividers (easily implemented with the
ICS674-01), the user can easily customize the
clock to lock to a wide variety of input frequencies.
Included on the ICS673-01 are an Output Enable
function that puts both outputs into a high-
impedance state, as well as a Power Down feature
that turns off the entire device.
Features
• Packaged in 16 pin narrow SOIC
• Access to VCO input and feedback paths of PLL
• VCO operating range up to 135 MHz (5V)
• Able to lock MHz range outputs to kHz range
inputs through use of external dividers
• Output Enable tri-states outputs
• Low skew output clocks
• Power Down turns off chip
• VCO predivide of 1 or 4
• 25 mA output drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• +3.3 V ±5% or +5 V ±10% operating voltage
• Industrial Temperature range available
• With the ICS674-01, forms a complete PLL
Block Diagram
VDD GND
23
CHGP VCOIN
VDD
REFIN
FBIN
PD
(entire chip)
Ic
UP
Phase/
Frequency
Detector
DOWN
Ic
VCO
1
MUX
÷4
0
Output
Buffer
÷2
Output
Buffer
CLK1
CLK2
CAP
SEL OE (both outputs)
MDS 673-01 D
1
Revision 022500
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•[phone]tel • www.icst.com