ICS673-01 Datasheet, PDF (2/9 Pages) Integrated Circuit Systems – PLL Building Block

Pin Assignment
ICS673-01
FBIN 1
VDD 2
VDD 3
GND 4
GND 5
GND 6
CHGP 7
VCOIN 8
16 REFIN
15 N C
14 CLK1
13 CLK2
12 PD
11 SEL
10 ^OE
9 ^CAP
16 pin narrow (150 mil) SOIC
ICS673-01
PLL Building Block
VCO Predivide Select Table
SEL
VCO Predivide
0
4
1
1
0 = connect pin directly to ground
1 = connect pin directly to VDD
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
FBIN
VDD
VDD
GND
GND
GND
CHGP
VCOIN
CAP
OE
SEL
PD
CLK2
CLK1
NC
REFIN
Type
CI
P
P
P
P
P
O
I
I
I
I
I
O
O
-
CI
Description
FeedBack INput. Connect feedback clock to this pin. Falling edge triggered.
VDD. Connect to +3.3 V or +5 V, and to VDD on pin 3.
VDD. Connect to VDD on pin 2.
Connect to ground.
Connect to ground.
Connect to ground.
CHarGe Pump output. Connect to VCOIN under normal operation.
Input to internal VCO.
Loop filter return.
Output Enable. Active high. Tri-states both outputs when low.
SELect pin for VCO pre-divide per table above.
Power Down. Turns off entire chip when this pin is low. Outputs stop low.
CLocK output 2. This is a low-skew divide by two version of CLK1.
CLocK output 1.
No Connect. Nothing is connected internally to this pin.
REFerence INput. Connect reference clock to this pin. Falling edge triggered.
Key: CI = clock input, I = Input, O = output, P = power supply connection
MDS 673-01 D
2
Revision 022500
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•[phone]tel • www.icst.com