ICS673-01 Datasheet, PDF (4/9 Pages) Integrated Circuit Systems – PLL Building Block

ICS673-01
PLL Building Block
External Components
Explanation of Operation
The ICS673 requires a minimum number of
external components for proper operation. A
decoupling capacitor of 0.01µF should be
connected between VDD and GND as close to the
ICS673 as possible. A series termination resistor of
33 Ω may be used for each clock output. Two
ceramic capacitors and a resistor are needed for the
external loop filter; calculations to determine the
proper values are shown on the following pages.
The capacitors must have very low leakage,
therefore high quality ceramic capacitors are
recommended. DO NOT use any type of polarized
or electrolytic capacitor. Ceramic capacitors should
have C0G or NP0 dielectric. Avoid high-K
dielectrics like Z5U and X7R; these and other
ceramics which have piezoelectric properties allow
mechanical vibration in the system to increase the
output jitter because the mechanical energy is
converted directly to voltage noise on the VCO
input.
The ICS673 is a PLL building block circuit that
includes an integrated VCO with a wide operating
range. While it can easily lock MHz frequencies to
other MHz frequencies, it is especially designed
for starting with a kHz frequency and generating a
frequency-locked MHz clock. Refer to Figure 1
below and to the Block Diagram on page 1.
The phase/frequency detector compares the falling
edges of the clocks connected to FBIN and
REFIN. It then generates an error signal to the
charge pump, which produces a charge
proportional to this error. The external loop filter
integrates this charge, producing a voltage that
then controls the frequency of the VCO. This
process continues until the edges of FBIN are
aligned with the edges of the REFIN clock, at
which point the output frequency will be locked to
the input frequency.
+3.3 or 5 V
C2
0.1µF
200kHz
RZ C1
SEL OE PD VDD CHGP VCOIN
CAP
REFIN
FBIN
ICS673-01
CLK1
GND ^CLK2
40 MHz
20 MHz
200kHz
÷100
Digital Divider
or ICS674-01
Figure 1. Typical Configuration; Generating 40 MHz from 200 kHz
MDS 673-01 D
4
Revision 022500
Printed 11/15/00
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