ICS527-03 Datasheet, PDF (7/8 Pages) Integrated Circuit Systems – Clock Slicer User Configurable PECL Output Zero Delay Buffer

Preliminary Information
ICS527-03
Clock Slicer User Configurable PECL Output Zero Delay Buffer
Parameter
Input Capacitance, except
PECLIN and FBIN
Short Circuit Current
On-chip pull-up resistor
Symbol
C_IN
I_OS
R_PU
Conditions
Min.
Typ.
5
Max. Units
pF
±70
mA
270
kΩ
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature 0 to +70°C
Parameter
Symbol
Conditions
Min.
Input Frequency
F_IN
1.5
Output Frequency, CLK1
F_OUT 0 to +70°C
2.5
-40 to +85°C
4
Output Rise Time
t_OR 0.8 to 2.0V, C_L=15pF
Output Fall Time
t_OF 2.0 to 0.8V, C_L=15pF
Output Duty Cycle (% high
time)
t_OD
Measured at VDD/2,
C_L=15pF
45
Power Down Time, PDTS low to
clocks tri-stated
Power Up ime, PDTS high to
clocks stable
Absolute Clock Period Jitter
One sigma Clock Period Jitter
Input to output skew
t_ja Deviation from mean
t_js
t_IO
PECLIN to CLK1,
Note 1
-250
Device to device skew
t_pi
Common PECLIN,
measured at FBIN
Typ.
1
1
Max.
200
160
140
50
55
50
10
± 90
40
250
0 500
Units
MHz
MHz
MHz
ns
ns
%
ns
ms
ps
ps
ps
ps
Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2.
MDS 527-03 B
7
Revision 122804
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