ICS527-03 Datasheet, PDF (1/8 Pages) Integrated Circuit Systems – Clock Slicer User Configurable PECL Output Zero Delay Buffer

Preliminary Information
ICS527-03
Clock Slicer User Configurable PECL Output Zero Delay Buffer
Description
The ICS527-03 is the most flexible way to generate an
output clock from an input clock with zero skew. The
user can easily configure the device to produce nearly
any output clock that is multiplied or divided from the
input clock. The part supports non-integer
multiplications and divisions. Using Phase-Locked
Loop (PLL) techniques, the device accepts an input
clock up to 200 MHz and produces an output clock up
to 160 MHz.
The ICS527-03 aligns rising edges on CLKIN with
FBPECL at a ratio determined by the reference and
feedback dividers.
For a PECL input and output clock with zero delay, use
the ICS527-04.
Features
• Packaged as 28 pin SSOP (150 mil body)
• Synchronizes fractional clocks rising edges
• CMOS in to PECL out
• Pin selectable dividers
• Zero input to output skew
• User determines the output frequency - no software
needed
• Slices frequency or period
• Input clock frequency of 1.5 MHz to 200 MHz
• Output clock frequencies from 2.5 MHz to 160 MHz
• Very low jitter
• Duty cycle of 45/55
• Operating voltage of 3.3 V
• Advanced, low power CMOS process
Block Diagram
CLKIN
Divide
by 2
R6:R0
7
1
Reference
0
Divider
FBPECL
FBPECL
Divide
by 2
1
Feedback
0
Divider
DIV2
7
F6:F0
2 VDD
Phase Comparator,
Charge Pump, and
Loop Filter
VCO
Output
Divider
2 _GND
PDTS
2
S1:S0
VDD
68 ohm
PECL
180 ohm
VDD
68 ohm
PECL
180 ohm
MDS 527-03 B
1
Revision 122804
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com