ICS527-03 Datasheet, PDF (5/8 Pages) Integrated Circuit Systems – Clock Slicer User Configurable PECL Output Zero Delay Buffer

Preliminary Information
ICS527-03
Clock Slicer User Configurable PECL Output Zero Delay Buffer
Multiple Output Example
In this example, an output clock of 125 MHz is used. Four copies of 50 MHz are required, de-skewed and
aligned to the 125 MHz input clock. The following solution uses the ICS554-01A which has buffers with low
pin to pin skew. The layout diagram below will produce the waveforms shown on the bottom.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No via’s should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via.
2) PECL termination networks should be located as
close to the outputs as possible.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS527-03. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
MDS 527-03 B
5
Revision 122804
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com