ICS527-03 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – Clock Slicer User Configurable PECL Output Zero Delay Buffer

Preliminary Information
ICS527-03
Clock Slicer User Configurable PECL Output Zero Delay Buffer
Pin Assignment
R5 1
R6 2
DIV2 3
S0 4
S1 5
VDD 6
FBPECL 7
FBPECL 8
GND 9
CLKIN 10
PDTS 11
F0 12
F1 13
F2 14
28
R4
27
R3
26
R2
25
R1
24
R0
23
VDD
22
PECL
21
PECL
20
GND
19
RES
18
F6
17
F5
16
F4
15
F3
28 pin 150 mil body SSOP
Pin Descriptions
Output Frequency and Output
Divider Table
S1 S0
00
01
10
11
Output Divider
2
4
8
1
Output Frequency (MHz)
10 - 80
5 - 40
2.5 - 20
20 -160
Pin
Number
1,2, 24-28
3
Pin
Name
R5, R6,
R0-R4
DIV2
4, 5
S0, S1
6, 23
7
8
9, 20
10
11
VDD
FPECL
FPECL
GND
CLKIN
PDTS
12-18
F0-F6
19
RES
21
PECL
22
PECL
Pin
Type
Input
Input
Input
Power
Input
Input
Power
Input
Input
Input
BIAS
Output
Output
Pin Description
Reference divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up.
Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based
on the table above. Internal pull-up.
Select pins for output divider determined by user. See table above. Internal
pull-up.
Connect to +3.3 V.
PECL feedback input.
Complementary PECL feedback input.
Connect to ground
Clock input.
Power Down. Active low. Turns off entire chip when low, both clock outputs are
tri-stated. Internal pull-up.
Feedback divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up
Resistor connection to VDD for setting level of PECL outputs.
Complementary PECL input clock.
PECL input clock.
MDS 527-03 B
2
Revision 122804
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