ICS527-03 Datasheet, PDF (4/8 Pages) Integrated Circuit Systems – Clock Slicer User Configurable PECL Output Zero Delay Buffer

Preliminary Information
ICS527-03
Clock Slicer User Configurable PECL Output Zero Delay Buffer
Typical Example
The following connection diagram shows the implementation of the example from the previous section.
This will generate a 50 MHz clock synchronously with a 40 MHz input. The layout diagram below will
produce the waveforms shown on the right.
VDD
0.01 F
R5
R6
DIV2
S0
S1
VDD
FBPECL
FBPECL
GND
CLKIN
PDTS
F0
F1
F2
R4
R3
R2
R1
R0
VDD
PECL
PECL
GND
RES
F6
F5
F4
F3
0.01 F
560
VDD
50 MHz
PECL output resistor network is not shown, but
is identical to PECL
40 MHz
(PECLIN shown)
50 MHz PECL
50 MHz PECL
Note: The series termination resistor is located before
the feedback
MDS 527-03 B
4
Revision 122804
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