ICSLV810 Datasheet, PDF (6/12 Pages) Integrated Circuit Systems – Buffer/Clock Driver

ICSLV810
Buffer/Clock Driver
Parameter
Input High Current
Input Capacitance
Output Capacitance
Symbol
Conditions
II
VDDC = max,
VIN = VDD (max)
CIN VIN = 0V, Note1
COUT V_OUT = 0V,
Note 1
Min.
Typ.
5
5.5
Max. Units
20
µA
6.0
pF
8.0
pF
Note1: This parameter is not tested, guaranteed by design.
AC Electrical Characteristics—Bank A
VDDA = 2.5 V, Ambient Temperature -40° C to +85° C
Parameter
Symbol
Conditions
Output Skew: skew between
outputs of same package
tSK(0)
CL = 3 pF,
RL = 500Ω
Figure 3
Pulse Skew: skew between
opposite transitions of same
output (tPLH-tPHL)
tSK(P)
CL = 3 pF,
RL = 500Ω
Figure 4
Propagation Delay
tpLH / tpHL
CL = 3 pF,
RL = 500Ω
Figure 2
Part to Part Skew
tSK(t)
CL = 3 pF,
RL = 500Ω
Figure 5
Output Rise Time
20% to 80%
tr(o)
CL = 3 pF,
RL = 500Ω
Output Fall Time
80% to 20%
tf(o)
CL = 3 pF,
RL = 500Ω
Additive Jitter
Duty Cycle
Measured at VDD/2
t_J
All Outputs
DC
CL = 3 pF,
RL = 500Ω
Duty Cycle, VDDA=1.8V
DC
Output Frequency Range
Min. Typ. Max. Units
-200
200 ps
-200
200 ps
1.5
2.6 3.5 ns
-650
650 ps
0.8
ns
0.8
ns
50
ps
45
55
%
40
50 60
%
1
133 MHz
MDS LV810 F
6
Revision 101305
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