ICS954204 Datasheet, PDF (6/16 Pages) Integrated Circuit Systems – Programmable Timing Control HubTM for Mobile P4TM Systems

Integrated
Circuit
Systems, Inc.
ICS954204
Absolute Max
Symbol Parameter
Min
VDD_A
3.3V Core Supply Voltage
VDD_In 3.3V Logic Input Supply Voltage GND - 0.5
Ts
Storage Temperature
-65
Tambient
Ambient Operating Temp
0
Tcase
Case Temperature
ESD prot
Input ESD protection
human body model
2000
Max
V_DD + 0.5V
V_DD + 0.5V
150
70
115
Units
V
V
°_C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
V_IH
3.3 V +/-5%
Input Low Voltage
Input High Current
Input Low Current
V_IL
3.3 V +/-5%
I_IH
V_IN = V_DD
I_IL1
V_IN = 0 V; Inputs with no pull-up
resistors
I_IL2
V_IN = 0 V; Inputs with pull-up
resistors
MIN
2
V_SS - 0.3
-5
-5
-200
TYP
Low Threshold Input High
Voltage
V_{IH_FS}
3.3 V +/-5%
0.7
Low Threshold Input Low
Voltage
3.3 V +/-5%
V_SS - 0.3
Operating Supply Current
I_DD3.3OP
Full Active, C_L = Full load;
275
Powerdown Current
I_DD3.3PD
all diff pairs driven
all differential pairs tri-stated
64
5
Input Frequency³
F_i
Pin Inductance¹
L_pin
V_DD = 3.3 V
14.31818
Input Capacitance¹
C_IN
C_OUT
Logic Inputs
Output pin capacitance
C_INX
X1 & X2 pins
Clk Stabilization^1,2
T_STAB
From V_DD Power-Up or de-
assertion of PD# to 1st clock
1.3
Modulation Frequency
Triangular Modulation
30
Tdrive_SRC
SRC output enable after
PCI_STOP de-assertion
Tdrive_PD
Differential output enable after
PD# de-assertion
Tfall_PD
PD# fall time of
Trise_PD
PD# rise time of
Tdrive_CPU_STOP
CPU output enable after
CPU_STOP de-assertion
Tfall_CPU_STOP
CPU_STOP fall time of
Trise_CPU_STOP#
CPU_STOP rise time of
SMBus Voltage
V_DD
2.7
Low-level Output Voltage
V_OL
SDATA, SCLK @ I_PULLUP
Current sinking
I_PULLUP
V_OL = 0.4 V
4
SCLK/SDATA
T_RI2C
(Max VIL - 0.15) to
SCLK/SDATA
Clock/Data Fall Time
T_FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
1_{Guaranteed by design, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3 _{Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet}
MAX
V_DD + 0.3
0.8
5
V_DD + 0.3
0.35
400
70
12
7
5
6
5
1.8
33
10
300
5
5
10
5
5
5.5
0.4
1000
300
UNITS
V
V
uA
uA
uA
V
V
mA
mA
mA
MHz
nH
pF
pF
pF
ms
kHz
ns
us
ns
ns
ns
ns
ns
V
V
mA
ns
ns
NOTES
1
1
1
1
1
1
1
3
1
1
1
1
1,2
1
1
1
1
2
1
1
2
1
1
1
1,3
1,3
0933D—03/16/05
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