ICS954204 Datasheet, PDF (15/16 Pages) Integrated Circuit Systems – Programmable Timing Control HubTM for Mobile P4TM Systems

Integrated
Circuit
Systems, Inc.
ICS954204
Table 5: PCI_STOP# Functionality
PCI_STOP#
CPU
CPU#
0
Normal
Normal
1
Normal
Normal
SRC
Normal
Iref*6 or Float
SRC#
Normal
Low
PCIF/PCI
33MHz
Low
DOT
Normal
Normal
DOT#
Normal
Normal
USB
48MHz
48MHz
REF
14.318MHz
14.318MHz
Table 6: PD Functionality
PD
CPU
0
Normal
1
Iref*2 or Float
CPU#
Normal
Float
SRC
Normal
Iref*2 or Float
SRC#
Normal
Float
PCIF/PCI
33MHz
Low
DOT
Normal
Iref*2 or Float
DOT#
Low
Float
USB
48MHz
Low
REF
14.318MHz
Low
Table 7: Tristate CPU Clock Control Truth Table
CPU_STOP
Signal
PD
CPU_STOP#
Tristate BIT
10
54
B5b[6, 5, 4]
CPU[2:0]
0
1
X
CPU[2:0]
0
0
0
CPU[2:0]
0
0
1
CPU[2:0]
1
X
X
CPU[2:0]
1
X
X
PD Tristate BIT
B5b[2,1,0]
X
X
X
1
0
Table 8: Tristate SRC Clock Control Truth Table
Signal
PCI/SRC_STOP
PD
PCI/SRC_STOP# _{Tristate BIT}
10
55
B5b7
SRC
0
1
X
SRC
0
0
0
SRC
0
0
1
SRC
1
X
X
SRC
1
X
X
PD Tristate BIT
B5b3
X
X
X
1
0
NON-STOP
OUTPUTS
Running
Running
Running
Driven @ I_REF X2
Tristate
STOPPABLE OUTPUTS
Running
Driven @ I_REF X6
Tristate
Driven @ I_REF X2
Tristate
NON-STOP
OUTPUTS
STOPPABLE OUTPUTS
Running
Running
Running
Driven @ I_REF X2
Tristate
Running
Driven @ IREF X6
Tristate
Driven @ I_REF X2
Tristate
Table 9: Tristate DOT Clock Control Truth Table
Signal
PD
PD Tristate BIT _{STOPPABLE OUTPUTS}
10
B4b6
DOT_96
0
X
Running
DOT_96
1
DOT_96
1
1
Driven @ I_REF X2
0
Tristate
Table10: CLKREQ# Clock Control Truth Table
Signal
SRC
SRC
SRC
SRC
SRC
PD
PCI/SRC_STOP#
10
55
0
1
0
1
0
0
0
0
1
X
CLKREQA#
CLKREQB#
33, 32
0
1
0
1
X
SELECTED OUTPUTS
Running
Tristate
Tristate
Stopped per B5b7
Stopped per B5b3
0933D—03/16/05
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