ICS954204 Datasheet, PDF (1/16 Pages) Integrated Circuit Systems – Programmable Timing Control HubTM for Mobile P4TM Systems

Integrated
Circuit
Systems, Inc.
ICS954204
Programmable Timing Control Hub™ for Mobile P4™ Systems
Recommended Application:
CK410M Compliant Main Clock with Integrated LCD Spread
Spectrum Clock.
Output Features:
• 2 - 0.7V current-mode differential CPU pairs
• 5 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
• 1 - 0.7V current-mode differential CPU/SRC selectable
pair
• 4 - PCI (33MHz)
• 2 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 1 - DOT, 96MHz, 0.7V current differential pair
• 1 - REF, 14.318MHz
• 1 - 0.7V current-mode differential LCD/SRC selectable
pair.
• PCI outputs cycle-cycle jitter < 500ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
• +/- 100ppm frequency accuracy on USB clocks
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA and
SRC
• Supports programmable spread percentage and
frequency
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Supports undriven differential CPU, SRC pair in PD#
for power management.
• CLKREQ pins to support SRC power management.
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC outputs cycle-cycle jitter < 125ps
Pin Configuration
Functionality
VDDPCI 1
GND 2
PCICLK3 3
PCICLK4 4
PCICLK5 5
GND 6
VDDPCI 7
ITP_EN/PCICLK_F0 8
*SELSRC_LCDCLK#/PCICLK_F1 9
Vtt_PwrGd#/PD 10
VDD48 11
FS_LA/USB_48MHz 12
GND 13
DOTT_96MHz 14
DOTC_96MHz 15
FS_LB/TEST_MODE 16
LCDCLK_SST/SRCCLKT0 17
LCDCLK_SSC/SRCCLKC0 18
SRCCLKT1 19
SRCCLKC1 20
VDDSRC 21
SRCCLKT2 22
SRCCLKC2 23
SRCCLKT3 24
SRCCLKC3 25
SRCCLKT4_SATA 26
SRCCLKC4_SATA 27
VDDSRC 28
56 PCICLK2
55 PCI/SRC_STOP#
CPU SRC PCI
FS_C FS_B FS_A _{MHz MHz MHz}
REF
MHz
USB
MHz
DOT
MHz
54 CPU_STOP#
53 FS_LC/TEST_SEL
52 REFOUT
51 GND
50 X1
49 X2
48 VDDREF
47 SDATA
46 SCLK
0
0
0 266.67 100.00 33.33 14.318 48.00
96.00
0
0
1 133.33 100.00 33.33 14.318 48.00
96.00
0
1
0 200.00 100.00 33.33 14.318 48.00
96.00
0
1
1 166.67 100.00 33.33 14.318 48.00
96.00
1
0
0 333.33 100.00 33.33 14.318 48.00
96.00
1
0
1 100.00 100.00 33.33 14.318 48.00
96.00
1
1
0 400.00 100.00 33.33 14.318 48.00
96.00
1
1
1 200.00 100.00 33.33 14.318 48.00
96.00
45 GND
44 CPUCLKT0
1. FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in the
43 CPUCLKC0
Input/Supply/Common Output Parameters Table for correct values. Also refer
42 VDDCPU
to the Test Clarification Table.
41 CPUCLKT1
40 CPUCLKC1
39 IREF
38 GNDA
2. ^{FS_B and FS_A are low-threshold inputs. Please see the V}IL_FS ^{and V}IH_FS
specifications in the Input/Supply/Common Output Parameters Table for
correct values.
37 VDDA
36 CPUCLKT2_ITP/SRCCLKT7
35 CPUCLKC2_ITP/SRCCLKC7
34 VDDSRC
33 CLKREQA#*
32 CLKREQB#*
31 SRCCLKT5
30 SRCCLKC5
29 GND
56-pin TSSOP
*100Kohm Pull-Up Resistor
0933D—03/16/05