ICS954204 Datasheet, PDF (14/16 Pages) Integrated Circuit Systems – Programmable Timing Control HubTM for Mobile P4TM Systems

Integrated
Circuit
Systems, Inc.
ICS954204
Table 3. Power-Up CLKREQ# Timing¹
Symbol
Parameter
Min
T_PVCRL
Power Valid to CLKREQ# Output Active
(Fig. 1)
T_SRCSTBL
SRC Clock Stablilzation Time from assertion
of CLKREQ# (Fig. 1)
1_{This timing is valid only after system clocks are stable.}
V_PCIEXDEV
Power Stable to Device
T_PVCRL
T_SRCSTBL
Max
100
800
CLKREQ#
SRCCLK
Figure 1. Power-Up CLKREQ# Timing
Table 4. CLKREQ# Control Timing
Symbol
Parameter
Min
Max
T_CRHoff
CLKREQ# De-asserted High to SRCCLK
Parked (Fig. 2)
0
T_CRHon
CLKREQ# Asserted LOW to SRCCLK
Active (Fig. 2)
0.4
Units
µs
µs
Units
µs
µs
CLKREQ#
SRCCLK
Figure 2. CLKREQ# Control Timing
CLKREQ# - Assertion (transition from logic “1” to logic “0”)
The impact of asserting the CLKREQ# pin is that the SRCCLK output will become active per the timing found in
Table 4. The clock will become active in a glitch free manner, providing a full cycle at the time it becomes active.
CLKREQ# - De-Assertion (transition from logic “0” to logic “1”)
The impact of asserting the CLKREQ# pin is that the SRCCLK output will become inactive setliing in the Tristate
condition per the timing found in Table 4. The clock will become inactive in a glitch free manner.
0933D—03/16/05
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