ICS954201 Datasheet, PDF (6/15 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for Mobile P4™ Systems

Integrated
Circuit
Systems, Inc.
ICS954201
Absolute Max
Symbol
Parameter
VDD_A
3.3V Core Supply Voltage
VDD_In 3.3V Logic Input Supply Voltage
Ts
Tambient
Tcase
ESD prot
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
GND - 0.5
-65
0
2000
Max
V_DD + 0.5V
V_DD + 0.5V
150
70
115
Units
V
V
°_C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS Notes
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V_IH
3.3 V +/-5%
2
V_IL
3.3 V +/-5%
V_SS - 0.3
I_IH
V_IN = V_DD
-5
I_IL1
V_IN = 0 V; Inputs with no pull-up
resistors
-5
I_IL2
V_IN = 0 V; Inputs with pull-up
resistors
-200
V_DD + 0.3 V
1
0.8
V1
5
uA 1
uA 1
uA 1
Low Threshold Input High
Voltage
V_{IH_FS}
3.3 V +/-5%
0.7
V_DD + 0.3 V
1
Low Threshold Input Low
Voltage
V_{IL_FS}
3.3 V +/-5%
V_SS - 0.3
0.35
Operating Supply Current
Powerdown Current
Input Frequency³
Pin Inductance¹
Input Capacitance¹
Clk Stabilization^1,2
I_DD3.3OP
I_DD3.3PD
F_i
L_pin
C_IN
C_OUT
C_INX
T_STAB
Full Active, C_L = Full load;
all diff pairs driven
all differential pairs tri-stated
V_DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From V_DD Power-Up or de-
assertion of PD# to 1st clock
278
400
67
70
4.8
12
14.31818
7
5
6
5
1.3
1.8
Modulation Frequency
Triangular Modulation
30
33
Tdrive_SRC
SRC output enable after
PCI_STOP de-assertion
8
10
Tdrive_PD
Differential output enable after
300
PD# de-assertion
Tfall_PD
PD# fall time of
5
Trise_PD
PD# rise time of
5
Tdrive_CPU_STOP
CPU output enable after
CPU_STOP de-assertion
8
10
Tfall_CPU_STOP
CPU_STOP fall time of
5
Trise_CPU_STOP#
CPU_STOP rise time of
5
SMBus Voltage
V_DD
2.7
Low-level Output Voltage
V_OL
SDATA, SCLK @ I_PULLUP
Current sinking
I_PULLUP
V_OL = 0.4 V
4
SCLK/SDATA
Clock/Data Rise Time
T_RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
5.5
0.4
1000
SCLK/SDATA
(Min VIH + 0.15) to
Clock/Data Fall Time
T_FI2C
(Max VIL - 0.15)
300
1_{Guaranteed by design, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3 _{Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet}
0819G—12/06/04
V1
mA
mA
mA
MHz 3
nH 1
pF 1
pF 1
pF 1
ms 1,2
kHz 1
ns 1
us 1
ns 1
ns 2
ns 1
ns 1
ns 2
V1
V1
mA 1
ns 1,3
ns 1,3
6