ICS954201 Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for Mobile P4™ Systems

Integrated
Circuit
Systems, Inc.
Pin Description
PIN # PIN NAME
1 VDDPCI
2 GND
3 PCICLK3
4 PCICLK4
5 PCICLK5
6 GND
7 VDDPCI
8 ITP_EN/PCICLK_F0
9 PCICLK_F1
10 Vtt_PwrGd#/PD
11 VDD48
12 USB_48MHz/FS_A
13 GND
14 DOTT_96MHz
15 DOTC_96MHz
16 FS_B/TEST_MODE
17 SRCCLKT0
18 SRCCLKC0
19 SRCCLKT1
20 SRCCLKC1
21 VDDSRC
22 SRCCLKT2
23 SRCCLKC2
24 SRCCLKT3
25 SRCCLKC3
26 SRCCLKT4_SATA
27 SRCCLKC4_SATA
28 VDDSRC
ICS954201
PIN
TYPE
PWR
PWR
OUT
OUT
OUT
PWR
PWR
I/O
OUT
IN
PWR
I/O
PWR
OUT
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
Free running PCI clock not affected by PCI_STOP# .
Vtt_PwrGd# is an active low input used to determine when
latched inputs are ready to be sampled. PD is an asynchronous
active high input pin used to put the device into a low power
state. The internal clocks, PLLs and the crystal oscillator are
stopped.
Power pin for the 48MHz output.3.3V
Frequency select latch input pin / Fixed 48MHz USB clock
output. 3.3V.
Ground pin.
True clock of differential pair for 96.00MHz DOT clock.
OUT Complement clock of differential pair for 96.00MHz DOT clock.
IN
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
3.3V tolerant input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values.
TEST_MODE is a real time input to select between Hi-Z and
REF/N divider mode while in test mode. Refer to Test
Clarification Table.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC/SATA pair.
Complement clock of differential SRC/SATA pair.
Supply for SRC clocks, 3.3V nominal
0819G—12/06/04
2