ICS954201 Datasheet, PDF (1/15 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for Mobile P4™ Systems

Integrated
Circuit
Systems, Inc.
ICS954201
Programmable Timing Control Hub™ for Mobile P4™ Systems
Recommended Application:
CK410M clock, Intel Yellow Cover part
Output Features:
• 2 - 0.7V current-mode differential CPU pairs
• 7 - 0.7V current-mode differential SRC pair for SATA and
PCI-E
• 1 - 0.7V current-mode differential CPU/SRC selectable
pair
• 4 - PCI (33MHz)
• 2 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 1 - DOT, 96MHz, 0.7V current differential pair
• 1 - REF, 14.318MHz
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA and
PCI-Express
• Supports spread spectrum modulation, 0 to -0.5%
down spread
• Supports CPU clocks up to 400MHz
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Supports undriven differential CPU, SRC pair in PD#
for power management.
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC outputs cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 500ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
• +/- 100ppm frequency accuracy on USB clocks
Pin Configuration
VDDPCI 1
GND 2
PCICLK3 3
PCICLK4 4
PCICLK5 5
GND 6
VDDPCI 7
ITP_EN/PCICLK_F0 8
PCICLK_F1 9
Vtt_PwrGd#/PD 10
VDD48 11
USB_48MHz/FS_A 12
GND 13
DOTT_96MHz 14
DOTC_96MHz 15
FS_B/TEST_MODE 16
SRCCLKT0 17
SRCCLKC0 18
SRCCLKT1 19
SRCCLKC1 20
VDDSRC 21
SRCCLKT2 22
SRCCLKC2 23
SRCCLKT3 24
SRCCLKC3 25
SRCCLKT4_SATA 26
SRCCLKC4_SATA 27
VDDSRC 28
Functionality
56 PCICLK2
55 PCI/SRC_STOP#
54 CPU_STOP#
53 FS_C/TEST_SEL
52 REFOUT
FS_C¹ FS_B² FS_A²
0
0
0
0
0
1
0
1
0
0
1
1
CPU
MHz
266.66
133.33
200.00
166.66
SRC
MHz
100.00
100.00
100.00
100.00
PCI REF
MHz MHz
33.33 14.318
33.33 14.318
33.33 14.318
33.33 14.318
USB
MHz
48.00
48.00
48.00
48.00
DOT
MHz
96.00
96.00
96.00
96.00
51 GND
50 X1
49 X2
48 VDDREF
1
0
0
333.33 100.00 33.33 14.318 48.00 96.00
1
0
1
100.00 100.00 33.33 14.318 48.00 96.00
1
1
0
400.00 100.00 33.33 14.318 48.00 96.00
1
1
1
RESERVED
14.318 48.00 96.00
47 SDATA
46 SCLK
45 GND
44 CPUCLKT0
43 CPUCLKC0
1. FS_C is a three-level input. Please see V_{IL_FS} and V_{IH_FS} specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_B and FS_A are low-threshold inputs. Please see the V_{IL_FS} and V_{IH_FS}
specifications in the Input/Supply/Common Output Parameters Table for correct values.
42 VDDCPU
41 CPUCLKT1
40 CPUCLKC1
39 IREF
38 GNDA
37 VDDA
36 CPUCLKT2_ITP/SRCCLKT7
35 CPUCLKC2_ITP/SRCCLKC7
34 VDDSRC
33 SRCCLKT6
32 SRCCLKC6
31 SRCCLKT5
30 SRCCLKC5
29 GND
56-pin SSOP & TSSOP
0819G—12/06/04