ICS954201 Datasheet, PDF (13/15 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for Mobile P4™ Systems

Integrated
Circuit
Systems, Inc.
ICS954201
SMBus Table: Test and Readback Control Register
Byte 6
Pin #
Name
Bit 7
-
Test Mode Selection
Bit 6
-
Test Clock Mod eEntry
Bit 5
-
Bit 4
-
REFOUT STRENGTH
Bit 3
-
PCI/SRC_STOP
Bit 2
-
Bit 1
-
Bit 0
-
FS_C
FS_B
FS_A
SMBus Table: Vendor & Revision ID Register
Byte 7
Pin #
Name
Bit 7
-
RID3
Bit 6
-
RID2
Bit 5
-
RID1
Bit 4
-
RID0
Bit 3
-
VID3
Bit 2
-
VID2
Bit 1
-
VID1
Bit 0
-
VID0
Control Function
Test Mode Selection
Test Mode
RESERVED
Strength Prog
Stop all PCI and SRC
clocks
readback
readback
readback
Type
RW
RW
RW
RW
R
R
R
0
Hi-Z
Disable
1X
Enabled
-
-
-
Control Function Type
0
R
-
REVISION ID
R
-
R
-
R
-
R
-
VENDOR ID
R
R
-
-
R
-
Test Clarification Table
Comments
· FS_C/TEST_SEL is a 3-level latched input.
o Power-up w/ V >= 2.0V to select TEST
o Power-up w/ V < 2.0V to have pin function as
FS_C.
· When pin is FS_C, VIH_FS and VIL_FS levels
apply.
· FS_B/TEST_MODE is a low-threshold input
o VIH_FS and VIL_FS levels apply.
o TEST_MODE is a real time input
· TEST_SEL can be invoked after power up
through SMBus B6b6.
o If TEST is selected by B6b6, only B6b7 controls
TEST_MODE. The FS_B/TEST_Mode pin is not
used.
· Power must be cycled to exit TEST.
HW
FS_C/TEST FS_B/TEST
_SEL
_MODE
HW PIN HW PIN
0
X
1
0
SW
TEST
ENTRY REF/N or
BIT
HI-Z
B6b6 B6b7 OUTPUT
0
X NORMAL
X
0
HI-Z
1
0
X
1
REF/N
1
1
X
0
REF/N
1
1
X
1
REF/N
0
X
1
0
HI-Z
0
X
1
1
REF/N
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
1
REF/N
Enable
2X
Disabled
-
-
-
PWD
0
0
0
1
1
LATCHED
LATCHED
LATCHED
1
PWD
-
0
-
0
-
0
-
1
-
0
-
0
-
0
-
1
0819G—12/06/04
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