ICS954201 Datasheet, PDF (12/15 Pages) Integrated Circuit Systems – Programmable Timing Control Hub™ for Mobile P4™ Systems

Integrated
Circuit
Systems, Inc.
ICS954201
SMBus Table: SRC Stop Control Register
Byte 3
Pin #
Name
Bit 7
36,35
SRCCLK7
Bit 6
33,32
SRCCLK6
Bit 5
31,30
SRCCLK5
Bit 4
26,27
SRCCLK4
Bit 3
Bit 2
24,25
22,23
SRCCLK3
SRCCLK2
Bit 1
19,20
SRCCLK1
Bit 0
17,18
SRCCLK0
Control Function Type
RW
Allow assertion of
RW
PCI_STOP# or setting of
PCI_STOP control bit in
RW
RW
SMBus register to stop ^RW
SRC clocks
RW
RW
RW
0
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
1
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
SMBus Table: Stop and Output Control Register
Byte 4
Pin #
Name
Bit 7
Bit 6
14,15
DOT_96MHz
Bit 5
Bit 4
9
PCI_F1
Bit 3
Bit 2
Bit 1
Bit 0
8
36,35
41,40
44,43
PCI_F0
CPUCLK2_ITP
CPUCLK1
CPUCLK0
Control Function Type
RESERVED
Driven in PD
RW
RESERVED
Allow assertion of
PCI_STOP# or setting of ^RW
PCI_STOP control bit in
SMBus register to stop _RW
PCICLK_F outputs
Allow assertion of
RW
CPU_STOP# to stop RW
CPUCLK outputs
RW
0
Driven
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
1
Hi-Z
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
SMBus Table: Output Control Register
Byte 5
Pin #
Name
Control Function Type
0
1
Driven in
Bit 7 SRCCLK(7:0)
SRC_STOP Drive Mode
PCI/SRC_STOP#
RW
Driven
Hi-Z
Bit 6
36,35
CPUCLK2_ITP_STOP Drive Mode
RW
Driven
Hi-Z
Bit 5
41,40
CPUCLK1_STOP Drive Mode ^{Driven in CPU_STOP#} RW
Driven
Hi-Z
Bit 4
44,43
CPUCLK0_STOP Drive Mode
RW
Driven
Hi-Z
Bit 3 SRCCLK(7:0)
SRC_PD Drive Mode
RW
Driven
Hi-Z
Bit 2
36,35
CPUCLK2_ITP_PD Drive Mode ^{Driven in Powerdown} RW
Driven
Hi-Z
Bit 1
41,40
CPUCLK1_PD Drive Mode
(PD)
RW
Driven
Hi-Z
Bit 0
44,43
CPUCLK0_PDDrive Mode
RW
Driven
Hi-Z
PWD
0
0
0
0
0
0
0
0
PWD
X
0
0
0
0
1
1
1
PWD
0
0
0
0
0
0
0
0
0819G—12/06/04
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