ICS94203 Datasheet, PDF (6/18 Pages) Integrated Circuit Systems – Programmable System Frequency Generator for PII/III™

ICS94203
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
-
27
-
28
-
37
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
24_48MHz
(Reserved)
48MHz
(Reserved)
SDRAM_F
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
-
0 Reserved
20
1 PCICLK6
19
1 PCICLK5
18
1 PCICLK4
17
1 PCICLK3
14
1 PCICLK2
13
1 PCICLK1
12
1 PCICLK0
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
38
1 SDRAM7
39
1 SDRAM6
40
1 SDRAM5
41
1 SDRAM4
44
1 SDRAM3
45
1 SDRAM2
46
1 SDRAM1
47
1 SDRAM0
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
9
1 3V66_2
7
1 3V66_0
8
1 3V66_1
56
1 REF
54
1 IOAPIC0
-
X Reserved
50
1 CPUCLK1
51
1 CPUCLK0
Byte 5: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
-
1 (Reserved)
-
1 (Reserved)
-
1 (Reserved)
-
1 (Reserved)
31
1 SDRAM11
32
1 SDRAM10
33
1 SDRAM9
34
1 SDRAM8
Byte 6: Byte Count Read Back Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin# PWD
Description
-
0 Reserved (Note)
-
0 Reserved (Note)
-
0 Reserved (Note)
-
0 Reserved (Note)
-
0 Reserved (Note)
-
1 Reserved (Note)
-
1 Reserved (Note)
-
0 Reserved (Note)
Note: Writing to this register will configure byte count and
how many bytes will be read back, default is 6 bytes.
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
6