ICS94203 Datasheet, PDF (10/18 Pages) Integrated Circuit Systems – Programmable System Frequency Generator for PII/III™

ICS94203
Byte 20: Output Dividers Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
X Output Divider MUX Control Bit23
X Output Divider MUX Control Bit22
X Output Divider MUX Control Bit21
X Output Divider MUX Control Bit20
X Output Divider MUX Control Bit19
X Output Divider MUX Control Bit18
X Output Divider MUX Control Bit17
X Output Divider MUX Control Bit16
Note: Changing bits in these registers results in
frequency divider ratio changes. Incorrect
configuration of group gear ratio can cause
system malfunction.
Byte 22: Output Rise/Fall Time Select Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
0 24,48MHz 0=Normal, 1=Weak
0 IOAPIC/REF 0=Normal, 1=Weak
0 PCI 0=Normal, 1=Weak
0 SDRAM_F 0=Normal, 1=Weak
0 SDRAM [0:11] 0=Normal, 1=Weak
0 3V66 0=Normal, 1=Weak
0 CPU1 0=Normal, 1=Weak
0 CPU0 0=Normal, 1=Weak
Notes:
1. PWD = Power on Default
Byte 21: ICS Reserved Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
1 3V66 to PCI Skew Bit3
0 3V66 to PCI Skew Bit2
1 3V66 to PCI Skew Bit1
1 3V66 to PCI Skew Bit0
0 3V66 to IOAPIC Skew Bit 3
1 3V66 to IOAPIC Skew Bit 2
1 3V66 to IOAPIC Skew Bit 1
0 3V66 to IOAPIC Skew Bit 0
Note: Each increment or decrement of bit 4 to 7 will introduce
100ps delay or advance on all of the above clocks.
Notes:
1. PWD = Power on Default
2. The power on default for byte 16-20 depends on the harware
(latch inputs FS[0:4]) or I²C (Byte 0 bit [1:7]) setting. Be sure
to read back and re-write the values of these 5 registers when
VCO frequency change is desired for the first pass.
3. If Byte 8 bit 7 is driven to "1" meaning programming is
intended, Byte 21-22 will lose their default power up value.
10