ICS94203 Datasheet, PDF (2/18 Pages) Integrated Circuit Systems – Programmable System Frequency Generator for PII/III™

ICS94203
General Description
The ICS94203 is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It provides all necessary
clock signals for such a system.
The ICS94203 belongs to ICS new generation of programmable system clock generators. It employs serial programming I²C interface
as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew,
changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over
clocking.
Spread spectrum typically reduces system EMI by 7dB to 8dB. This simplifies EMI qualification without resorting to board design
iterations or costly shielding.
Pin Configuration
PIN NUMBER
1, 6, 10, 16, 25,
35, 43, 48
3
PIN NAME
VDD
X1
4
2, 5, 11, 15, 26,
36, 42, 49
9, 8, 7
12
13
14
X2
GND
3V66 [2:0]
PCICLK0¹
FS0
PCICLK1¹
FS1
SEL24_48#
PCICLK2
TYPE
DESCRIPTION
PWR
IN
OUT
3.3V power supply
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load cap (33pF)
PWR Ground pins for 3.3V supply
OUT
OUT
IN
OUT
IN
3.3V Fixed 66MHz clock outputs for HUB
3.3V PCI clock output, with Synchronous CPUCLKS
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock output, with Synchronous CPUCLKS
Logic input frequency select bit. Input latched at power on.
IN 24/48MHz frequency select pin for pin 27
OUT 3.3V PCI clock output, with Synchronous CPUCLKS
20, 19, 18, 17
21
PCICLK [6:3]
RATIO_0
22
PD#
23
24
27
28
29
30
37
31, 32, 33, 34,
38, 39, 40, 41,
44, 45, 46, 47
50, 51
52
53, 55
54
56
SCLK
SDATA
FS2
24_48MHz
FS3
48MHz
RATIO_1
RESET
SDRAM_F
SDRAM [11:0]
CPUCLK [1:0]
GNDL
VDDL
IOAPIC
FS4
REF¹
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
OUT
IN
IN
I/O
IN
OUT
IN
OUT
OUT
OUT
OUT
Output to chipset, replacing the BSEL0 signals orginally from the processor.
Asynchronous active low input pin used to power down the device into a low power state. The
internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power
down will not be greater than 3ms.
Clock input of I²C input
Data input for I²C serial input.
Logic input frequency select bit. Input latched at power on.
3.3V 24_48MHz output Default is 24MHz.
Logic input frequency select bit. Input latched at power on.
3.3V Fixed 48MHz clock output for USB.
Output to chipset, replacing the BSE1 signals orginally from the processor.
Real time system reset signal for frequency ratio change or watchdog timmer timeout.
This signal is active low.
3.3V SDRAM output can be turned off through I²C
OUT 3.3V output. All SDRAM outputs can be turned off through I²C
OUT
PWR
PWR
OUT
IN
OUT
2.5V Host bus clock output. Output frequency derived from FS pins.
Ground for 2.5V power supply for CPU & APIC
2.5V power suypply for CPU, IOAPIC
2.5V clock outputs running at 16.67MHz.
Logic input frequency select bit. Input latched at power on.
3.3V, 14.318MHz reference clock output.
2