ICS94203 Datasheet, PDF (1/18 Pages) Integrated Circuit Systems – Programmable System Frequency Generator for PII/III™

Integrated
Circuit
Systems, Inc.
ICS94203
Programmable System Frequency Generator for PII/III™
Recommended Application:
810/810E and Solano (815) type chipset
Output Features:
• 2 - CPUs @ 2.5V
• 13 - SDRAM @ 3.3V
• 3 - 3V66 @ 3.3V
• 7 - PCI @3.3V
• 1 - 24/48MHz@ 3.3V
• 1 - 48MHz @ 3.3V fixed
• 1 - REF @3.3V, 14.318MHz
Features:
• Programmable ouput frequency
• Gear ratio change detection
• Real time system reset output
• Spread spectrum for EMI control
with programmable spread percentage
• Watchdog timer technology to reset system
if over-clocking causes malfunction.
• Support power management through PD#.
• Uses external 14.318MHz crystal
• FS pins for frequency select
Key Specifications:
• CPU Output Jitter: <250ps
• IOAPIC Output Jitter: <500ps
• 48MHz, 3V66, PCI Output Jitter: <500ps
• CPU Output Skew: <175ps
• PCI Output Skew: <500ps
• 3V66 Output Skew <175ps
• For group skew timing, please refer to the
Group Timing Relationship Table.
Power Groups
VDDA, GNDA = Core PLL, Xtal
VDD48, GND48 = 48MHz, Fixed PLL
Pin Configuration
VDDA
1
GNDA
2
X1
3
X2
4
GND3V66
5
VDD3V66
6
3V66-0
7
3V66-1
8
3V66-2
9
VDDPCI
10
GNDPCI
11
1_*FS0/PCICLK0
12
1_*FS1/PCICLK1
13
1_{*SEL24_48#/PCICLK2}
14
GNDPCI
15
VDDPCI
16
PCICLK3
17
PCICLK4
18
PCICLK5
19
PCICLK6
20
RATIO_0
21
PD#
22
SCLK
23
SDATA
24
VDD48
25
GND48
26
*FS2/24_48MHz
27
1_*FS3/48MHz
28
56
REF/FS4*¹
55 VDDLAPIC
54
IOAPIC0¹
53 VDDLCPU
52 GNDLCPU
51 CPUCLK0
50 CPUCLK1
49 GNDSDR
48 VDDSDR
47 SDRAM0
46 SDRAM1
45 SDRAM2
44 SDRAM3
43 VDDSDR
42 GNDSDR
41 SDRAM4
40 SDRAM5
39 SDRAM6
38 SDRAM7
37 SDRAM_F
36 GNDSDR
35 VDDSDR
34 SDRAM8
33 SDRAM9
32 SDRAM10
31 SDRAM11
30 RESET#
29 RATIO_1
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2
X1
XTAL
X2
OSC
PLL1
Spread
Spectrum
FS(4:0)
PD#
SEL24_48#
SDATA
SCLK
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
SDRAM
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
48MHz
24_48MHz
REF
2 ^{CPUCLK (1:0)}
12 ^{SDRAM (11:0)}
SDRAM_F
IOAPIC
PCICLK (6:0)
7
3V66 (2:0)
3
RESET#
RATIO_0
RATIO_1
94203 Rev B 02/13/01
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.