ICS87946-01 Datasheet, PDF (6/13 Pages) Integrated Circuit Systems – LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS87946-01
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE
5B.
AC
CHARACTERISTICS,
V_DD
=
3.3V±5%,
V
DDX
=
2.5V±5%,
TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Input Frequency
tp_LH
Propagation Delay,
Low to High; NOTE 1
tp_HL
Propagation Delay,
High to Low; NOTE 1
f ≤ 250MHz
f ≤ 250MHz
250
3.2
3.2
tsk(b) Bank Skew; NOTE 2, 7
Measured on rising edge at V_DDx/2
100
tsk(o) Output Skew; NOTE 3, 7
Measured on rising edge at V_DDx/2
200
tsk(w)
Multiple Frequency Skew;
NOTE 4, 7
Measured on rising edge at V_DDx/2
350
tsk(pp) Part-to-Part Skew; NOTE 5, 7 Measured on rising edge at V_DDx/2
500
t
Output Rise Time; NOTE 6
20% to 80%
600
R
t_F
Output Fall Time; NOTE 6
20% to 80%
600
odc
Output Duty Cycle
50
t_EN
Output Enable Time;
NOTE 6
f = 10MHz
t_DIS
Output Disable Time;
NOTE 6
f = 10MHz
All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the V_DD/2 of the input to V_DDx/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
Measured at V_DDx/2.
NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages
and equal load conditions.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDx/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ns
ps
ps
ps
ps
ps
ps
%
ns
ns
87946AY-01
www.icst.com/products/hiperclocks.html
6
REV. A JANUARY 2, 2002