ICS87946-01 Datasheet, PDF (10/13 Pages) Integrated Circuit Systems – LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS87946-01
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V /2 is
DD
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
DD
CLK_IN
C1
0.1uF
V_DD
R1
1K
+
V_REF
-
R2
1K
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87946AY-01
www.icst.com/products/hiperclocks.html
10
REV. A JANUARY 2, 2002