ICS87946-01 Datasheet, PDF (2/13 Pages) Integrated Circuit Systems – LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS87946-01
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
1
Name
nc
Type
Unused
Description
No connect.
2
V_DD
Power
Positive supply pins. Connect to 3.3V.
3
PCLK
Input Pulldown Non-inverting differential LVPECL clock input.
4
nPCLK
Input
Pullup Inverting differential LVPECL clock input.
5
6
7
8, 11, 15,
20, 24, 27,
31
DIV_SELA
DIV_SELB
DIV_SELC
GND
Input
Input
Input
Pulldown
Pulldown
Pulldown
Controls frequency division for Bank A outputs.
LVCMOS interface levels.
Controls frequency division for Bank B outputs.
LVCMOS interface levels.
Controls frequency division for Bank C outputs.
LVCMOS interface levels.
Power
Power supply ground. Connect to ground.
9, 13, 17
10, 12,
14, 16
V_DDC
QC0, QC1,
QC2, QC3
Power
Output
Positive supply pins for Bank C outputs. Connect to 3.3V or 2.5V.
Bank C outputs. LVCMOS interface levels.
7Ω typical output impedance.
18, 22
19, 21, 23
V_DDB
QB2, QB1,
QB0
Power
Output
Positive supply pins for Bank B outputs. Connect to 3.3V or 2.5V.
Bank B outputs. LVCMOS interface levels.
7Ω typical output impedance.
25, 29
26, 28,
30
V_DDA
QA2, QA1,
QA02,
Power
Output
Positive supply pins for Bank A outputs. Connect to 3.3V or 2.5V.
Bank A outputs. LVCMOS interface levels.
7Ω typical output impedance.
32
MR/nOE
Input
Pulldown
Master reset and output enable. Resets outputs to tristate.
Enables and disables all outputs. LVCMOS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
C
Input Capacitance
IN
R_PULLUP
Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
C_PD
Power Dissipation Capacitance (per output)
R_OUT
Output Impedance
*NOTE: V_DDx denotes V_DDA, V_DDB, V_DDC.
Test Conditions
V_DD, *V_DDx = 3.465V
Minimum
Typical
51
51
TBD
7
Maximum
4
Units
pF
KΩ
KΩ
pF
Ω
TABLE 3. FUNCTION TABLE
MR/nOE
1
0
0
0
0
0
0
Inputs
DIV_SELA
DIV_SELB
X
X
0
X
1
X
X
0
X
1
X
X
X
X
DIV_SELC
X
X
X
X
X
0
1
QA0 - QA2
Hi Z
fIN/1
fIN/2
Active
Active
Active
Active
87946AY-01
www.icst.com/products/hiperclocks.html
2
Outputs
QB0 - QB2
Hi Z
Active
Active
fIN/1
fIN/2
Active
Active
QC0 - QC3
Hi Z
Active
Active
Active
Active
fIN/1
fIN/2
REV. A JANUARY 2, 2002