ICS87946-01 Datasheet, PDF (1/13 Pages) Integrated Circuit Systems – LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS87946-01
LOW SKEW ÷1, ÷2
LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87946-01 is a low skew, ÷1, ÷2 Clock
,&6
Generator and a member of the HiPerClockS™
HiPerClockS™ _{family of High Performance Clock Solutions from}
ICS. The ICS87946-01 has one LVPECL clock
input pair. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels. The low impedance
LVCMOS outputs are designed to drive 50Ω series or parallel
terminated transmission lines. The effective fanout can be in-
creased from 10 to 20 by utilizing the ability of the outputs to
drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
The ICS87946-01 is characterized at 3.3V core/3.3V output
and 3.3V core/2.5V output. Guaranteed bank, output and part-
to-part skew characteristics make the ICS87946-01 ideal for
those clock distribution applications demanding well defined
performance and repeatability.
FEATURES
• 10 single ended LVCMOS outputs, 7Ω typical output
impedance
• LVPECL clock input pair
• PCLK, nPCLK supports the following input levels:
LVPECL, CML, SSTL
• Maximum input frequency: 250MHz
• Output skew: 200ps (maximum)
• Part-to-part skew: 500ps (typical)
• Multiple frequency skew: 350ps (maximum)
• 3.3V input, outputs may be either 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
PCLK
nPCLK
DIV_SELA
DIV_SELB
DIV_SELC
MR/nOE
÷1
0
÷2
1
0
1
0
1
QA0 - QA2
QB0 - QB2
QC0 - QC3
nc
VDD
PCLK
nPCLK
DIV_SELA
DIV_SELB
DIV_SELC
GND
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4 _ICS87946-01 21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
GND
QB0
VDDB
QB1
GND
QB2
VDDB
VDDC
32-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87946AY-01
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 2, 2002