ICS87931I Datasheet, PDF (6/14 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, V_DDA = V_DDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
f_REF
Parameter
Input Reference Frequency
NOTE: Input reference frequency is limited by
the divider selection and the VCO lock range.
Test Conditions
Minimum Typical
Maximum
150
Units
MHz
TABLE 7. AC CHARACTERISTICS, V_DDA = V_DDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions Minimum Typical
QAx, QBx
÷2
f_MAX
Output Frequency QAx, QBx, QCx
÷4
QCx
÷6
t_PD
Propagation Delay; ^{CLK1 to EXT_FB}
NOTE 1
CLK0, nCLK0 to EXT_FB
fref = 50MHz,
FB = ÷ 8
-375
-100
-200
50
tsk(o) Output Skew; NOTE 2, 4
Same Frequency
Different Frequency
tjitter(cc) Cycle-to-Cycle Jitter; NOTE 4
f_VCO
PLL VCO Lock Range
t_R/t_F
Output Rise Time; NOTE 3
odc
Output Duty Cycle
220
0.8V to 2.0V
0.1
45
t_LOCK
PLL Lock Time
t_PZL, t_PZH Output Enable Time; NOTE 3
2
t_PLZ, t_PHZ Output Disable Time; NOTE 3
2
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to V_DDO/2 of the output
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
150
120
80
-50
200
300
400
100
480
1
55
10
10
8
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
MHz
ns
%
ms
ns
ns
87931BYI
www.icst.com/products/hiperclocks.html
6
REV. A JUNE 23, 2003