ICS87931I Datasheet, PDF (10/14 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
SCHEMATIC EXAMPLE
Figure 4A shows a schematic example of using an ICS87931I. It
is recommended to have one decouple capacitor per power pin.
Each decoupling capacitor should be located as close as pos-
sible to the power pin. The low pass filter R7, C11 and C16 for
clean analog supply should also be located as close to the VDDA
pin as possible.
VDD
R7
10 - 15
VDD
R1 43
Zo = 50
VDD
U1
3.3V
C16
10u
C11
0.01u
Zo = 50 Ohm
POWER_DN
Zo = 50 Ohm
1
2
3
4
5
6
7
8
nc
VDDA
POW ER _D N
CLK1
nMR
CLK0
nCLK0
GND
GND
QB0
QB1
VDDO
EXTFB_SEL
CLK_SEL
PLL_SEL
nc
24
23
22
21
20
19
18
17
R3 R4
1K 1K
R5
3.3V PECL Driv er
1K
R8
R9
ICS87931I
50
50
Logic Input Pin Examples
R10
Set Logic
Set Logic
50
VDD
VDD
Input to
Input to
’1’
’0’
RU1
1K
RU2
Not Install
R2 43
Zo = 50
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
(U1-13)
VDD
VDD=3.3V
C1
0.1uF
SP = Space (i.e. not intstalled)
(U1-21) (U1-28)
C2
0. 1uF
C3
0.1uF
Receiv er
Receiv er
FIGURE 4A. ICS87931I SCHEMATIC EXAMPLE
87931BYI
www.icst.com/products/hiperclocks.html
10
REV. A JUNE 23, 2003