ICS87931I Datasheet, PDF (1/14 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
GENERAL DESCRIPTION
The ICS87931I is a low voltage, low skew
,&6
LVCMOS/LVTTL Clock Multiplier/Zero Delay
HiPerClockS™ _{Buffer and a member of the HiPerClockS™ family}
of High Performance Clock Solutions from ICS.
With output frequencies up to 150MHz, the
ICS87931I is targeted for high performance clock applications.
Along with a fully integrated PLL, the ICS87931I contains fre-
quency configurable outputs and an external feedback input for
regenerating clocks with “zero delay”.
Selectable clock inputs, CLK1 and differential CLK0, nCLK0
support redundant clock applications. The CLK_SEL input de-
termines which reference clock is used. The output divider val-
ues of Bank A, B and C are controlled by the DIV_SELA,
DIV_SELB and DIV_SELC, respectively.
For test and system debug purposes, the PLL_SEL input al-
lows the PLL to be bypassed. When LOW, the nMR input re-
sets the internal dividers and forces the outputs to the high im-
pedance state.
The effective fanout of the ICS87931I can be increased to 12
by utilizing the ability of each output to drive two series termi-
nated transmission lines.
FEATURES
• Fully integrated PLL
• 6 LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock
for redundant clock applications
• Maximum output frequency: 150MHz
• VCO range: 220MHz to 480MHz
• External feedback for “zero delay” clock regeneration
• Output skew, Same Frequency: 300ps (maximum)
• Output skew, Different Frequency: 400ps (maximum)
• Cycle-to-cycle jitter: 100ps (maximum)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Pin compatible with MPC931
PIN ASSIGNMENT
BLOCK DIAGRAM
POWER_DN ^Pullup
PLL_SEL ^Pullup
CLK_SEL ^Pulldown
CLK1 ^Pullup
nc
VDDA
POWER_DN
CLK1
nMR
CLK0
nCLK0
GND
32 31 30 29 28 27 26 25
1
24
2
23
3 ICS87931I 22
4
32-Lead LQFP
21
5 ^{7mm x 7mm x 1.4mm} 20
6
package body ₁₉
7
Y package
18
Top View
8
17
9 10 11 12 13 14 15 16
GND
QB0
QB1
VDDO
EXTFB_SEL
CLK_SEL
PLL_SEL
nc
CLK0 ^Pullup
nCLK0 ^None
EXTFB_SEL ^Pulldown
EXT_FB ^Pullup
DIV_SELA Pulldown
DIV_SELB Pulldown
CLK_EN0
CLK_EN1
DIV_SELC
Pullup
Pullup
Pulldown
nMR ^Pullup
87931BYI
1
0
PHASE
DETECTOR
VCO
0
0
1
÷2 1
LPF
1
÷8
0
POWER-ON RESET
DISABLE
LOGIC
www.icst.com/products/hiperclocks.html
1
÷2/÷4
÷2/÷4
÷4/÷6
QA0
QA1
QB0
QB1
QC0
QC1
REV. A JUNE 23, 2003