ICS87931I Datasheet, PDF (2/14 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 9, 17, 32
nc
Unused
No connect.
2
V_DDA
Power
Analog supply pin.
3
POWER_DN Input
Pullup
Controls the frequency being fed to the output dividers.
LVCMOS / LVTTL interface levels.
4
CLK1
Input Pullup Clock input. LVCMOS / LVTTL interface levels.
Active LOW Master reset. When logic LOW, the internal dividers are
5
nMR
Input Pullup reset causing the outputs to go low. When logic HIGH, the internal
dividers and the outputs are enabled. LVCMOS / LVTTL interface levels.
6
CLK0
Input Pullup Non-inverting differential clock input.
7
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock input. V_CC/2 default when left floating.
8, 16, 24,25
GND
Power
Power supply ground.
10, 11
12
CLK_EN0,
CLK_EN1
EXT_FB
Input
Input
Pullup
Pullup
Controls the enabling and disabling of the clock outputs. See Table 3B.
LVCMOS / LVTTL interface levels.
External feedback. When LOW, selects internal feedback.
When HIGH, selects EXT_FB. LVCMOS / LVTTL interface levels.
13, 21, 28
14, 15
18
19
V_DDO
QC0, QC1
PLL_SEL
CLK_SEL
Power
Output
Input
Input
Output supply pins.
Bank C clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Selects between the PLL and reference clocks as the input to the
Pullup output dividers. When HIGH, selects PLL. When LOW, bypasses
the PLL. LVCMOS / LVTTL interface levels.
Clock select input. Selects the Phase Detector Reference.
Pulldown When LOW, selects CLK0, nCLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
20
EXTFB_SEL Input Pulldown External feedback select. LVCMOS / LVTTL interface levels.
22, 23
26, 27
29
30
31
QB1, QB0
QA1, QA0
DIV_SELA
DIV_SELB
DIV_SELC
Output
Output
Input
Input
Input
Bank B clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Bank A clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Pulldown
Determines output divider values for Bank A as described in Table 4A.
LVCMOS / LVTTL interface levels.
Pulldown
Determines output divider values for Bank B as described in Table 4A.
LVCMOS / LVTTL interface levels.
Pulldown
Determines output divider values for Bank C as described in Table 4A.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
C
PD
R_OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
V , V = 3.465V
DDA DDO
Minimum
Typical
4
51
51
12
7
Maximum
Units
pF
KΩ
KΩ
pF
Ω
87931BYI
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 23, 2003