ICS854057 Datasheet, PDF (6/13 Pages) Integrated Circuit Systems – 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION

Integrated
Circuit
Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
PARAMETER MEASUREMENT INFORMATION
V
DD
2.5V±5%
POWER SUPPLY
+ Float GND -
LVDS
V
DD
nPCLK0:
nPCLK3
Qx ^SCOPE
V
PP
PCLK0:
PCLK3
nQx
GND
Cross Points
V
CMR
2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nPCLKx
PCLKx
nPCLKy
PCLKy
nQ
Q
INPUT SKEW
t_PD2
t_PD1
tsk(i)
tsk(i) = |t_PD1 - t_PD2|
nPCLK0:
nPCLK3
PCLK0:
PCLK3
nQ
Q
t_PD
nQ
PART 1
Q
nQ
PART 2
Q
t sk(pp)
PART-TO-PART SKEW
nQ
Q
t _PW
t
PERIOD
odc = ^{t PW} x 100%
t _PERIOD
PROPAGATION DELAY
854057AG
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
www.icst.com/products/hiperclocks.html
6
REV. A JULY 18, 2005