ICS854057 Datasheet, PDF (10/13 Pages) Integrated Circuit Systems – 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION

Integrated
Circuit
Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from PCLK to ground.
OUTPUTS:
LVDS OUTPUT
All unused LVDS outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
SCHEMATIC EXAMPLE
Figure 4shows a schematic example of the ICS854057. In this
example, the PCLK0/nPCLK0 and PCLK1/nPCLK1 inputs are
used. The decoupling capacitors should be physically located
near the power pin.
VDD
LVDS
Zo = 50
Zo = 50
VDD
Zo = 50
LVPECL Zo = 50
VDD
R1
1K
R1
1K
VDD
U1
ICS854057
VDD
R1
680
1
2
3
4
5
6
7
8
9
10
VDD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
nPCLK1
GND
20
VDD
PCLK3
VT3
nPCLK3
Q
nQ
PCLK2
VT2
nPCLK2
19
18
17
16
15
14
13
12
11
GND
VDD
R3
680
R2
R4
680
680
R6
18
(U1,1)
VDD (U1,20)
C1
0.1u
C2
0.1u
VD D =2.5V
Zo = 50
R5
100
Zo = 50
+
-
LVDS
FIGURE 4. EXAMPLE ICS854057 LVDS SCHEMATIC
854057AG
www.icst.com/products/hiperclocks.html
10
REV. A JULY 18, 2005