ICS854057 Datasheet, PDF (4/13 Pages) Integrated Circuit Systems – 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION

Integrated
Circuit
Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
TABLE 4D. LVDS DC CHARACTERISTICS, V_DD = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
V_OD
Δ V_OD
V
OS
Δ V_OS
Differential Output Voltage
V_OD Magnitude Change
Offset Voltage
V_OS Magnitude Change
Minimum
225
1.125
Typical
325
4
1.25
5
Maximum
425
35
1.375
25
Units
mV
mV
V
mV
TABLE 5. AC CHARACTERISTICS, V_DD = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
f_MAX
t_PD
tjit
tsk(i)
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Input Skew
622.08MHz,
12kHz - 20MHz
>2
300
66
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
50
47
≤ 700MHz
49
mux_ISOLATION MUX Isolation
f = 500MHz
-55
NOTE: All parameters are measured at IJ1.9GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the output is measured
at the differential cross point.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
800
40
200
250
53
51
Units
GHz
ps
fs
ps
ps
ps
%
%
dBm
854057AG
www.icst.com/products/hiperclocks.html
4
REV. A JULY 18, 2005