ICS950602 Datasheet, PDF (5/16 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for PII/III

Integrated
Circuit
Systems, Inc.
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Bit7
-
X FS4 Read back
Bit6
-
X FS3 Read back
Bit5
-
X FS2 Read back
Bit4
-
X FS1 Read back
Bit3
-
X FS0 Read back
Bit2
48
1 CPUCLK0
Bit1
47
1 CPUCLK1
Bit0 44, 43
1 CPUCLKT, CPUCLKC
Description
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Bit7
39
1 SDRAM6
Bit6
10
1 PCICLK_F
Bit5
17
1 PCICLK5
Bit4
16
1 PCICLK4
Bit3
15
1 PCICLK3
Bit2
14
1 PCICLK2
Bit1
13
1 PCICLK1
Bit0
11
1 PCICLK0
Description
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
Bit7
-
0 RESET gear shift detect 1 = Enable, 0 = Disable
Bit6
-
0 SEL24_48: 0 = 24, 1 = 48
Bit5
27
1 48MHz
Bit4
26
1 24_48MHz
Bit3
-
0 Reserved
Bit2 31, 30
1 SDRAM (4:5)
Bit1 34, 33
1 SDRAM (2:3)
Bit0 37, 36
1 SDRAM (0:1)
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
X
MULTSEL Read back
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0469B—12/18/02
Description
5
ICS950602