ICS950602 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for PII/III

Integrated
Circuit
Systems, Inc.
ICS950602
General Description
The ICS950602 is a single chip clock solution for VIA Mobile PL133T and PLE133T chipsets. It provides all necessary clock
signals for such a system.
The ICS950602 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I²C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With
all these programmable features, ICS' TCH makes motherboard testing, tuning and improvement very simple.
Pin Description
PIN NUMBER
1, 6, 12, 23,
32, 38, 42,
5, 9, 29, 35
2
3
PIN NAME
GND
VDD
FS2
REF1
REF0
4
Vtt_PWRGD#
7
X1
8
X2
10
11
17, 16, 15, 14, 13
18
19
FS4
PCICLK_F
FS3
PCICLK0
PCICLK (5:1)
SDRAM_IN
CPU_STOP#
20
PCI_STOP#
21
PD#
22
MULTSEL
24
SDATA
25
SCLK
FS1
26
48_24MHz
FS0
27
48MHz
28
30, 31, 33, 34, 36,
37, 39
AVDD48
SDRAM (5:0, 6)
40
I REF
41
43
44
45
46
47, 48
0469B—12/18/02
RESET#
CPUCLKC
CPUCLKT
VDDCPU_3.3
VDDCPU_2.5
CPUCLK (1:0)
TYPE
DESCRIPTION
PWR Ground pins for 3.3V supply
PWR
IN
OUT
OUT
IN
IN
OUT
3.3V power supply
Logic input frequency select bit. Input latched at power on.
3.3V, 14.318MHz reference clock output.
3.3V, 14.318MHz reference clock output.
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (4:0)
are valid and are ready to be sampled (active low)
Crystal input, has internal load cap (33pF) and feedback resistor from X2
Crystal output, nominally 14.318MHz. Has internal load cap (33pF)
IN Logic input frequency select bit. Input latched at power on.
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN
I/O
IN
IN
OUT
IN
OUT
PWR
3.3V PCI clock output
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock output
3.3V PCI clock outputs
SDRAM buffer input pin.
Stops all CPUCLKs clocks at logic 0 level, when input low
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
3.3V LVTTL input for selecting the current multiplier for CPU outputs.
Data pin for I²C circuitry 5V tolerant
Clock pin for I²C circuitry 5V tolerant
Logic input frequency select bit. Input latched at power on.
Selectable 48 or 24MHz output
Logic input frequency select bit. Input latched at power on.
3.3V Fixed 48MHz clock output.
3.3V analog power supply for 48 or 24MHz outputs.
OUT
OUT
OUT
OUT
OUT
PWR
PWR
OUT
SDRAM clock outputs.
This pin establishes the reference current for the CPUCLK pairs. This pin requires
a fixed precision resistor tied to ground in order to establish the appropriate
current.
Real time system reset signal for frequency value or watchdog timer timeout. This
signal is active low.
"Complementary" clock of differential pair CPU outputs. These are current outputs
and external resistors are required for voltage bias.
"True" clock of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
3.3V power for CPU differential clocks.
2.5V power for CPU clocks.
CPU clock outputs.
2