ICS9248-128 Datasheet, PDF (5/16 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers

ICS9248-128
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
40
41
43
-
PWD
1
1
1
1
1
1
1
X
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
CPUCLK3
CPUCLK2
CPUCLK1
FS0#
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
-
13
12
11
10
8
PWD
X
1
1
1
1
1
1
1
Description
FS1#
PCICLK_F
(Reserved)
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
28
29
31
32
34
35
37
38
PWD
1
1
1
1
1
1
1
1
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
25
26
15
17
18
20
21
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
24/14MHz
48MHz
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
47
-
44
46
2
PWD
1
X
1
1
X
1
1
1
Description
(Reserved)
FS2#
(Reserved)
IOAPIC
SD_SEL#
REF2
REF1
REF0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
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