ICS9248-128 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers

ICS9248-128
Pin Descriptions
Pin number
1
2^1,2
3,9,16,22,
27,33,39
4
5
6,14
7^1,2
8^1,2
13, 12, 11, 10
15,28,29,31,32,
34,35,37,38
Pin name
V DDR/X
REF0
M ode
GND
X1
X2
V DDP CI
FS1
PCICLK_F
PCICLK 0
FS2
P CICLK (4:1)
SDRAM 12,
S DRAM (7:0)
SDRAM 11
Type
P ower
Output
Input
D escription
Is olated 3.3 V power for crys tal & referenc e
3.3V, 14.318 MHz reference clock output.
Function select pin, 1=desk top mode, 0=mobile mode. Latched input.
Power 3.3 V Ground
Input
Output
P ower
Input
Output
Output
Input
Output
14.318 MHz crystal input
14.318 MHz crystal output
3.3 V power for the PCI clock outputs
Logic input frequency s elec t bit. Input latched at power-on.
3.3 V free running PCI c loc k output, will not be stopped by the P CI_STOP #
3.3 V P CI cloc k outputs, generating tim ing requirem ents for P entium II
Logic input frequency s elec t bit. Input latched at power-on.
3.3 V P CI cloc k outputs, generating tim ing requirem ents for P entium II
Output SDRA M c lock outputs . Frequency is s elec ted by S D-S el latched input.
Output SDRA M c lock outputs . Frequency is s elec ted by S D-S el latched input.
17 ¹
CP U_S T O P #
As ynchronous ac tiv e low input pin used to s top the CP UCLK in low state,
Input all other clocks will continue to run. The CPUCLK will have a "Turnon" latency
of at least 3 CPU clocks.
18 ¹
19
20 ¹
21 ¹
23
24
25 ^1,2
SDRAM 10
P CI-S TOP#
V DDS D/C
SDRAM 9
S DRA M _S TO P #
SDRAM 8
P D#
SDATA
S CLK
S E L24_14#
SIO
Output
Input
P ower
Output
Input
Output
Input
Input
Input
Input
Output
SDRA M c lock outputs . Frequency is s elec ted by S D-S E L latched input.
Synchronous active low input used to stop the PCICLK in a low state. It will not
effect PCICLK_F or any other outputs.
3.3 V power for SDRAM outputs and core
SDRA M c lock outputs . Frequency is s elec ted by S D-S el latched input.
As ynchronous ac tiv e low input us ed to stop the S DRA M in a low s tate.
It will not effect any other outputs.
SDRA M c lock outputs . Frequency is s elec ted by S D-S el latched input.
As ynchronous ac tiv e low input pin used to power down the devic e into a low
power state. The internal c lock s are dis abled and the V CO and the c ry stal are
stopped. The latency of the power down will not be greater than 3ms.
Data input for I²C serial input.
Clock input of I²C input
This input pin controls the frequency of the S IO. If logic 0 at power on
SIO= 14.318 M Hz . If logic 1 at power-on S IO= 24M Hz .
Super I/O output. 24 or 14.318 M Hz. S electable at power-up by S E L24_14M Hz
26 ^1,2
30,36
40,41,43
42
44 ^1,2
45
46 ^1,2
47
48
FS0
48 MHz
V DDS DR
CP UCLK (3:1)
V DDLCP U
REF2
CP U3.3#_2.5
GNDL
REF1
SD_SEL#
IOAPIC
V DDLA P IC
Input
Output
P ower
0utput
P ower
Output
Input
P ower
Output
Input
Output
P ower
Logic input frequency s elec t bit. Input latched at power-on.
3.3 V 48 MHz clock output, fixed frequency clock typically used with
USB devices
3.3 V power for SDRAM outputs
2.5 V CPU and Host clock outputs
2.5 V power for CPU
3.3V, 14.318 MHz reference clock output.
This pin selects the operating voltage for the CPU. If logic 0 at power on
CP U= 3.3 V and if logic 1 at power on CPU= 2.5 V operating voltage.
2.5 V Ground for the IOAPIC or CPU
3.3V, 14.318 MHz reference clock output.
This input pin controls the frequency of the S DRA M .
2.5V fixed 14.318 MHz IOAPIC clock outputs
2.5 V power for IOAPIC
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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