ICS8535-21 Datasheet, PDF (5/14 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8535-21
LOW SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, V_CC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
266
t_PD
Propagation Delay; NOTE 1
IJ 266MHz
1.0
1.6
tsk(o) Output Skew; NOTE 2, 5
20
tsk(pp) Part-to-Part Skew; NOTE 3, 5
300
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 4
156.25MHz @ Integration
Range: 12KHz - 20MHz
0.03
t_R/t_F
Output Rise/Fall Time
20% to 80% @ 50MHz
300
600
odc
Output Duty Cycle
IJ 200MHz
45
55
All parameters measured at IJ 266MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the V_CC/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: Driving only one input clock.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ps
ps
ps
ps
%
8535AG-21
www.icst.com/products/hiperclocks.html
5
REV. A OCTOBER 20, 2004