ICS8535-21 Datasheet, PDF (1/14 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8535-21
LOW SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS8535-21 is a low skew, high performance
1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout
HiPerClockS™ _{buffer and a member of the HiPerClockS™ fam-}
ily of High Performance Clock Solutions from
ICS. The ICS8535-21 has two single-ended clock
inputs. The single-ended clock input accepts LVCMOS or
LVTTL input levels and translate them to 3.3V LVPECL lev-
els. The clock enable is internally synchronized to eliminate
runt clock pulses on the output during asynchronous asser-
tion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8535-21 ideal for those applications demand-
ing well defined performance and repeatability.
FEATURES
• 2 differential 3.3V LVPECL outputs
• Selectable CLK0 or CLK1 inputs for redundant
and multiple frequency fanout applications
• CLK0 or CLK1 can accept the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 266MHz
• Translates LVCMOS and LVTTL levels to
3.3V LVPECL levels
• Output skew: 20ps (maximum)
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 1.6ns (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
CLK_EN
CLK0
0
CLK1
1
CLK_SEL
D
Q
LE
PIN ASSIGNMENT
VEE 1
14 VCC
CLK_EN 2 13 Q0
CLK_SEL 3 12 nQ0
Q0
nQ0
CLK0 4 11 nc
VEE 5
10 Q1
Q1
nQ1
CLK1 6
VCC 7
9 nQ1
8 VCC
ICS8535-21
14-Lead TSSOP
4.4mm x 5.0mm x 0.92mm body package
G Package
Top View
8535AG-21
www.icst.com/products/hiperclocks.html
1
REV. A OCTOBER 20, 2004