ICS8535-21 Datasheet, PDF (10/14 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8535-21
LOW SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8535-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8535-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_CC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)_MAX = V_{CC_MAX} * I_{EE_MAX} = 3.465V * 50mA = 173.25mW
• Power (outputs)_MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 x 30mW = 60mW
Total Power (3.465V, with all outputs switching) = 173.25mW + 60mW = 233.25mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockS^TM devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming a
moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 85.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.233W * 85.5°C/W = 90°C. This is well below the limit of 125°C.
This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply
voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ_JA FOR 14-PIN TSSOP, FORCED CONVECTION
θ_JA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
146.4°C/W
93.2°C/W
200
125.2°C/W
85.5°C/W
500
112.1°C/W
81.2°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8535AG-21
www.icst.com/products/hiperclocks.html
10
REV. A OCTOBER 20, 2004