ICS950810 Datasheet, PDF (4/19 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950810
Power Groups
(Analog)
VDDA = PLL1
VDD48 = 48MHz, PLL
VDDREF = VDD for Xtal, POR
Truth Table
(Digital)
VDDPCI
VDD3V66
VDDCPU
FS2
FS1
FS0
CPU
(MHz)
3V66
(5:0)
(MHz)
PCI_F
PCI
(MHz)
X
0
0
166.66 66.66
33.33
X
0
1
100.00 66.66
33.33
X
1
0
200.00 66.66
33.33
X
1
1
133.33 66.66
33.33
Mid
0
0
Tristate Tristate Tristate
Mid
0
1
TCLK/2 TCLK/4 TCLK/8
Mid
1
0 Reserved Reserved Reserved
Mid
1
1 Reserved Reserved Reserved
REF0
(MHz)
14.318
14.318
14.318
14.318
Tristate
TCLK
Reserved
Reserved
USB/DOT
(MHz)
48.00
48.00
48.00
48.00
Tristate
TCLK/2
Reserved
Reserved
Maximum Allowed Current
Condition
Powerdown Mode
(PWRDWN# = 0)
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
All static inputs = Vdd or GND
25mA
Full Active
360mA
Host Swing Select Functions
MULTISEL0
0
1
Board Target
Trace/Term Z
-
50 ohms
Reference R,
Iref =
V_DD/(3*Rr)
-
Rr = 475 1%,
Iref = 2.32mA
Output
Current
Voh @ Z
-
-
Ioh = 6* I REF 0.7V @ 50
NOTE: MULTSEL0 = 0 not supported in ICS950810. Refer to ICS950805 for Buffered Mode support.
0472F—01/12/04
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