ICS950810 Datasheet, PDF (2/19 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950810
Pin Configuration
PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN NAME
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_2
3V66_3
3V66_4
3V66_5
25
PD#
26
VDDA
27
GND
TYPE
PWR
IN
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
PWR
PWR
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Ground pin for 3V outputs.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCICLK_F and PCICLK, nominal 3.3V
Ground pin for 3V outputs.
PCI clock outputs.
PCI clock outputs.
PCI clock outputs.
PCI clock outputs.
Power supply for PCICLK_F and PCICLK, nominal 3.3V
Ground pin for 3V outputs.
PCI clock outputs.
PCI clock outputs.
PCI clock outputs.
Power pin for the 3V66 clocks.
Ground pin for 3V outputs.
66MHz outputs at 3.3V.
66MHz outputs at 3.3V.
66MHz outputs at 3.3V.
66MHz input/output at 3.3V.
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
3.3V power for the PLL core.
Ground pin for 3V outputs.
0472F—01/12/04
2