ICS950810 Datasheet, PDF (3/19 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950810
Pin Configuration (Continued)
PIN
NUMBER
PIN NAME
TYPE
28
Vtt_PWRGD#
IN
29
SDATA
I/O
30
SCLK
IN
31
GND
PWR
32
VDD3V66
PWR
33
3V66_0
OUT
34
PCI_STOP#
IN
35
3V66_1/VCH_CLK
OUT
36
GND
PWR
37
VDD48
PWR
38
48MHz_DOT
OUT
39
48MHz_USB
OUT
40
FS2
IN
41
GND
PWR
42
IREF
OUT
43
MULTSEL0
IN
44
CPUCLKC2
OUT
45
CPUCLKT2
OUT
46
VDDCPU
PWR
47
GND
PWR
48
CPUCLKC1
OUT
49
CPUCLKT1
OUT
50
VDDCPU
PWR
51
CPUCLKC0
OUT
52
CPUCLKT0
OUT
53
CPU_STOP#
IN
54
FS0
IN
55
FS1
IN
56
REF
OUT
DESCRIPTION
This 3.3V LVTTL input is a level sensitive strobe used to determine when
FS[2:0] and MULTISEL0 inputs are valid and are ready to be sampled.
(active low)
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
Ground pin for 3V outputs.
Power pin for the 3V66 clocks.
66MHz outputs at 3.3V.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
input low
Selectable 48MHz non-SSC or 66MHz SSC clock output
Ground pin for 3V outputs.
Power for 48MHz output buffers and fixed PLL core.
48MHz output clock
48MHz output clock
Frequency select pin.
Ground pin for 3V outputs.
This pin festablishes the reference current for the CPUCLK pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the
appropriate current.
3.3V LVTTL input for selection the current multiplier for CPU outputs
"Complementary" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks,3.3V nominal
Ground pin for 3V outputs.
"Complementary" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks,3.3V nominal
"Complementary" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
This asynchronous input halts to active low level when driven low.
Frequency select pin.
Frequency select pin.
14.318 MHz reference clock.
0472F—01/12/04
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