953002CFLF Datasheet, PDF (4/35 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor

Integrated
Circuit
Systems, Inc.
ICS953002
General Description
ICS953002 is a 56-pin clock chip for P4 type processors with PCI-Express.
The ICS953002 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I²C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
X1
XTAL
X2
FS (4:0)
SCLK
Sel24_48#
SDATA
MODE0
VTTPWRGD#
PD#
Turbo#
Control
Logic
PLL2
Frequency
Dividers
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
48MHz
24_48MHz
REF (1:0)
CPUCLKT (1:0)
CPUCLKC (1:0)
CPUCLKT2_ITP/PCIEXT0
CPUCLKC2_ITP/PCIEXC0
3V66 (2:0)
PCICLK (5:0)
PCI-EXT (5:1)
PCI-EXC (5:1)
RESET#
I REF
0924—11/18/09
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