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953002CFLF Datasheet, PDF (24/35 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor
Integrated
Circuit
Systems, Inc.
ICS953002
I2C Table: Byte Count Register
Byte 8
Pin #
Name
Bit 7
-
BC7
Bit 6
-
BC6
Bit 5
-
BC5
Bit 4
-
BC4
Bit 3
-
BC3
Bit 2
-
BC2
Bit 1
-
BC1
Bit 0
-
BC0
Control Function
Byte Count
Programming b(7:0)
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
PWD
0
0
0
0
1
1
1
1
I2C Table: WD Time Control Register
Byte 9
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
-
WDEN
-
WDSEN
-
WD Alarm Status
-
WD Soft Status
-
WDTCtrl
Bit 2
-
Bit 1
-
Bit 0
-
WD2
WD1
WD0
Control Function
Watchdog Enable
Watchdog Soft Reset
Enable
WD Alarm Status
WD Soft Reset Status
Watch Dog Time base
Control
WD Timer Bit 2
WD Timer Bit 1
WD Timer Bit 0
Type
RW
RW
R
R
RW
RW
RW
RW
0
Disable
Disable
Normal
Normal
290ms Base
1
Enable
Enable
Alarm
Alarm
1160ms Base
These bits represent X*290ms (or 1.16S)
the watchdog timer waits before it goes to
alarm mode. Default is 7 X 290ms = 2s.
PWD
0
0
x
x
0
1
1
1
I2C Table: M/N Programming & WD Safe Frequency Control Register
Byte 10
Pin #
Name
Control Function Type
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
WD Safe Freq
Source
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
Reserved
RW
Reserved
RW
WD Safe Freq Source RW
RW
RW
Watch Dog Safe Freq
Programming bits
RW
RW
RW
0
-
-
B10b(4:0)
1
-
-
Latch Inputs
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
PWD
1
1
0
0
0
0
0
0
I2C Table: PLL1 Frequency Control Register
Byte 11
Pin #
Name
Control Function
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
N Div8
N Div9
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Divider Prog bit 8
N Divider Prog bit 9
M Divider
Programming bits
Type
0
1
RW
RW
The decimal representation of M and N
RW Divier in Byte 11 and 12 will configure the
RW PLL1 VCO frequency. Default at power
RW
up = latch-in or Byte 0 Rom table.
RW VCO Frequency = 14.318 x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
RW
RW
PWD
X
X
X
X
X
X
X
X
0924—11/18/09
24