953002CFLF Datasheet, PDF (3/35 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor

Integrated
Circuit
Systems, Inc.
ICS953002
Pin Description (Continued)
PIN #
PIN NAME
29 3V66_0
30 GND3V66
31 SCLK
32 GNDPCIEX
33
PCIEXC5/PCI_PCIEX_STO
P#*
TYPE
OUT
PWR
IN
PWR
OUT
34 PCIEXT5/CPU_STOP#*
OUT
35 PCIEXC4
36 PCIEXT4
37 PCIEXC3
38 PCIEXT3
39 VDDPCIEX
40 GNDPCIEX
41 PCIEXC2
42 PCIEXT2
43 PCIEXC1
44 PCIEXT1
45 VDDPCIEX
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
46 CPUCLKC2_ITP/PCIEXC0
OUT
47 CPUCLKT2_ITP/PCIEXT0
48 SDATA
49 VDDCPU
50 CPUCLKC1
51 CPUCLKT1
52 GNDCPU
53 CPUCLKC0
54 CPUCLKT0
OUT
I/O
PWR
OUT
OUT
PWR
OUT
OUT
55 IREF
56 GND
OUT
PWR
DESCRIPTION
3.3V 66.66MHz clock output
Ground pin for the 3.3V 66MHz clocks
Clock pin of SMBus circuitry, 5V tolerant.
Ground pin for the PCI-EX outputs
Complement clock of differential PCI_Express pair. / Active low signal that
stops all PCI and PCIEX clocks besides the free running clocks
True clock of differential PCI_Express pair./Stops all CPUCLK besides the
free running clocks
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
Ground pin for the PCI-EX outputs
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias./
Complement clock of differential PCIEX pair
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias. / True clock of
differential PCIEX pair
Data pin for SMBus circuitry, 5V tolerant.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin for the CPU outputs
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
Ground pin.
0924—11/18/09
3