953002CFLF Datasheet, PDF (23/35 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor

Integrated
Circuit
Systems, Inc.
ICS953002
I²C Table: Output Control Register
Byte 4
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
PCIEXCLKT/C5
-
PCIEXCLKT/C4
-
PCIEXCLKT/C3
-
PCIEXCLKT/C2
-
PCIEXCLKT/C1
-
CPUCLK2/PCIEX0
-
CPUCLKT/C1
-
CPUCLKT/C0
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
I²C Table: Device Control Register
Byte 5
Pin #
Name
Control Function Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
AGP/PCI PLL Cntrl AGP/PCI PLL Source RW
-
PCIEX PLL Cntrl PCIEX PLL Source
RW
-
Reserved
Reserved
RW
-
Reserved
Reserved
RW
-
ASYNC1
3V66/PCI Async Freq RW
-
ASYNC0
Prog bits
RW
-
Reserved
Reserved
RW
-
Reserved
Reserved
RW
I²C Table: Reserved Register
Byte 6
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
I²C Table: Vendor ID Register
Byte 7
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
REVID3
REVID2
REVID1
REVID0
VID3
VID2
VID1
VID0
Control Function
Revision ID
Revision ID
Revision ID
Revision ID
Vendor ID
Vendor ID
Vendor ID
Vendor ID
Type
R
R
R
R
R
R
R
R
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
0
PLL1
PLL1
-
-
00 = PLL1/2
01 = 66.0/33.0
-
-
0
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
0001 = ICS
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
PLL2
PLL2
-
-
10 = 75.4/37.7
11 = 88.0/44.0
-
-
1
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
1
1
1
1
1
1
1
1
PWD
0
0
1
1
0
0
1
1
PWD
0
0
0
0
0
0
0
0
PWD
0
0
0
0
0
0
0
1
0924—11/18/09
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