953002CFLF Datasheet, PDF (22/35 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor

Integrated
Circuit
Systems, Inc.
ICS953002
I²C Table: Device Control Register
Byte 0
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
FS Source
Reserved
ROD
FS4
FS3
FSL2
FSL1
FSL0
I²C Table: Device Control Register
Byte 1
Pin #
Name
Bit 7
-
Bit 6
-
SS_EN1
SS_EN2
Bit 5
-
M/N Enable bit
Bit 4
-
Bit 3
-
CPUFS4
CPUFS3
Bit 2
-
Bit 1
-
CPUFS2
CPUFS1
Bit 0
-
CPUFS0
B1b[4:3] = 00 is invalid
I²C Table: Output Control Register
Byte 2
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
REF0
REF1
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
I²C Table: Output Control Register
Byte 3
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
48MHz
24_48MHz
3V66_2
3V66_1
3V66_0
SEL24_48MHz
ITP_EN
Mode 0
Control Function
Frequency H/W IIC
Select
Reserved
Reset On Demand
Freq/Div Sel Bit 4
Freq/Div Sel Bit 3
Freq/Div Sel Bit 2
Freq/Div Sel Bit 1
Freq/Div Sel Bit 0
Type
0
1
RW
Latch Inputs
IIC
RW
-
-
RW
Disable
Enable
RW
RW
See Table 1b: PLL2 AGP/PCI Frequency
RW
Selection Table
RW
RW
PWD
0
1
0
latch
latch
latch
latch
latch
Control Function
PLL1 Spread Enable
PLL2 Spread Enable
M/N Programming
Enable bit
PLL1 VCO Sel b4
PLL1 VCO Sel b3
PLL1 VCO Sel b2
PLL1 VCO Sel b1
PLL1 VCO Sel b0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
OFF
OFF
Disable
1
ON
ON
Enable
See Table 1a: PLL1 Rom VCO
Frequency Selection Table
PWD
1
1
0
X
X
0
0
0
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Select
Output Select
Output Select
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
48MHz
PCIEXCLKT/C0
PCIEXCLKT/C5
1
Enable
Enable
Enable
Enable
Enable
24MHz
CPUCLKT/C2
CPU_STOP/PCI_P
CIEX_STOP
PWD
1
1
1
1
1
Latch
Latch
Latch
0924—11/18/09
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