ICS952607 Datasheet, PDF (2/21 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor

Integrated
Circuit
Systems, Inc.
ICS952607
Advance Information
Pin Description
PIN
# ^{PIN NAME}
1 *FS1/REF0
2 *FS0/REF1
3 REF2
4 VDDREF
5 X1
6 X2
7 GND
8 **FS2/PCICLK_F0
9 **FS4/PCICLK_F1
10 PCICLK_F2
11 VDDPCI
12 GND
13 ^^PCICLK0
14 PCICLK1
15 PCICLK2
16 PCICLK3
17 VDDPCI
18 GND
19 PCICLK4
20 PCICLK5
21 **Sel24_48#/24_48MHz
22 **FS3/48MHz_0
23 48MHz_1
24 GND
25 VDD48
26 3V66_3/VCH
27 3V66_2
28 VDD3V66
29 GND
30 3V66_1
31 3V66_0
32 SCLK
33 SDATA
PIN TYPE DESCRIPTION
I/O
I/O
OUT
PWR
IN
OUT
PWR
I/O
I/O
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
I/O
I/O
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input,nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24mHz, 0 =
48MHz.
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
48MHz clock output.
Ground pin.
Power for 24 & 48MHz output buffers and fixed PLL core.
3.3V 66.66MHz clock output / 48MHz VCH clock output.
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of I2C circuitry 5V tolerant
Data pin for I2C circuitry 5V tolerant
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
34 VttPWR_GD/PD#
IN
are valid and are ready to be sampled. This is an active high input. / Asynchronous
active low input pin used to power down the device into a low power state.
35 VDD
36 SRCCLKC
37 SRCCLKT
38 GND
39 CPUCLKC0
40 CPUCLKT0
41 VDDCPU
42 CPUCLKC1
43 CPUCLKT1
44 GND
45 Reset#
46 IREF
47 GND
48 VDDA
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
PWR
Power supply, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
"Complementary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
"Complementary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Ground pin.
Real time system reset signal for frequency gear ratio change or watchdog timer
timeout. This signal is active low.
This pin establishes the reference current for the CPUCLK pairs. This pin requires a
fixed precision resistor tied to ground in order to establish the appropriate current.
Ground pin.
3.3V power for the PLL core.
0734—07/16/04
2